1. Field of the Invention
This invention relates to a method and process for attaching an electrically conductive substance onto substrates and, in particular, a process that provides attachment of solder bumps onto substrates, with particular advantages in applications in which a pitch of less than 400 microns is required.
2. Background
Enormous research and development resources are spent the world over in the perennial search for low cost, high volume methods of producing and assembling integrated circuits or "chips". An integral piece of chip assembly is making electrical interconnections. Solder bumped flip chip technology has become extremely popular because it provides a tiny semiconductor die with terminations all on one side (in the form of solder pads or bumps); after the chip surface has been treated, it can be flipped over and attached to a matching substrate. To make the connection, flip chip technology includes techniques for affixing bumps of electrically conductive material onto substrates, including boards, packages and chips. Flip chip bumping techniques have also proven useful in tape automated bonding (TAB). Other applications for solder bumps have included opto-electronics and silicon-on-silicon interconnects.
Flip chip technology presents a number of advantages that make it a preferred form of electronic interconnect. Flip chip provides improved electrical performance. Flip chip interconnections are the most efficient electrical interconnections for high frequency applications such as main frames and computer workstations. In addition to efficiency in function, the flip chip is efficient in form because of its small size. As devices of ever greater power are reduced in size, flip chip provides the smallest interconnect option. Other advantages include easier thermal management and reduced EMI emmissions and reduced RFI susceptibility.
Solder bump flip chip assembly can be made compatible with well-established Surface Mount Technology (SMT). (For a thorough introduction to SMT, please refer to the Handbook of Surface Mount Technology, Stephen W. Hinch, Longman Scientific & Technical, UK, 1988.) With the appropriate choice of solder bump metallurgy, an SMT assembly line can simultaneously assemble both flip chip and surface mount packages on a product passing through the line. This compatibility provides the utilization of an installed base of SMT assembly lines as well as the flexibility of designing packages incorporating flip chip into larger SMT packages. Perhaps the most telling advantage of flip chip over other packaging technologies is its lower cost. Flip chip eliminates an entire level of interconnect--the package level (see Steps B through E in FIG. 2). By eliminating the package level, system cost is significantly reduced. In the IC business generally, the potential cost savings justify investments in multi-million dollar flip chip technology research.
The primary way of making flip chip interconnects is with solder bumps. Solder bumps have been applied by evaporation, electroplating, stencil printing and serial methods. However, each of these methods has particular limitations and much research has been and is being performed to overcome the limitations of each of these methods.
For the past three decades, companies such as IBM have used evaporation to form high lead (Pb) bumps for flip chip applications. One major disadvantage of evaporation is the high cost: at least ten million dollars worth of capital equipment is required. Processing costs are also high due to tooling and mask costs, process delays, low throughput, low yields, and necessarily frequent manual removal of hazardous lead waste. Finally, alloy compositions are limited because many metals are not suitable for evaporation. Especially limiting is the fact that the deposition rate of tin (Sn) is such that it cannot readily be evaporated. A high tin alloy (63Sn-37Pb, that is "eutectic") is highly desirable as a bumping material, because the melting point of eutectic tin (T.sub.m =183 degrees C.) is compatible with existing SMT materials and processes (usually performed at 200-210 degrees C.). By contrast, the melting point of lead is 327 degrees C., a temperature that would melt many of the organic materials used in SMT (e.g. epoxy circuit boards, whose maximum temperature is 230 degrees C., and other components).
There is no shortage of patents that have issued covering improvements in the evaporation process. Because the evaporation process involves vaporizing lead and allowing the lead to deposit on all surfaces, both masked and unmasked, the cleaning of the metal shadow mask is messy and hazardous. The metal mask can only be reused three or four times before it is no longer cleanable and must be discarded. The waste lead, including the lead-encrusted metal mask, poses environmental and worker safety problems as well as escalates manufacturing expense. A recent patent, U.S. Pat. No. 5,152,878, addressed the problem of mask cleaning and presented some labor saving cleaning techniques. However, although improvements may speed bumping and reduce labor costs to a certain degree, the equipment required for evaporation remains costly, and the hazards of the waste lead are ever-present.
Whereas the evaporation technique is fraught with the hazards of vaporizing lead, electroplating is a wet technique using chemical baths as the medium in which to deposit bumps. The chemical baths contain lead and other hazardous materials that pose a handling and disposal problem. Moreover, electroplating is limited in efficiency because it is a batch process. Thus, volume production faces the attendant challenges of an equipment intense serial process and, as IC manufacturers are all too keenly aware, cost is governed by the production volume or capacity limits. Other disadvantages of electroplating include difficulty in alloy composition control, problems in consistently achieving acceptable bump height at small bump pitches, and difficulty in the elimination of surface impurities.
Stencil printing (also known as screen printing), depicted in FIG. 2A, is by far the simplest approach, at least conceptually, but has posed seemingly insurmountable limitations on bump size and pitch. (See, generally, Handbook of Surface Mount Technology, ibid, pp 245-260).
As depicted in FIG. 2A, stencil printing involves placing a mask 10 or screen on a substrate 12, slathering on a solder paste on top of the mask, using a squeegee 16 to squeegee the paste, which serves to force paste into all the apertures in the mask and to scrape off the excess paste, and removing the mask prior to re-flowing the solder paste. Re-flow is essentially controlled melting in order that the small spheres of metal that compose the solder paste coalesce to form the electronic interconnect.
Packing more interconnects on smaller chip has created a need for smaller bumps with smaller pitch (pitch being the distance between the centers of two adjacent bumps). Conventional stencil printing methods have had a lower pitch limit of 400 microns, primarily due to the limitations on well-established stencil aspect ratio (about 2.5:1) of aperture width relative to mask thickness. This limit is the result of the interplay of the spacing of holes in and thickness of the stencil and the physical and chemical characteristics of the solder paste. The well-known pitch limitation convinced IC manufacturers that stencil printing had no future in the majority of flip chip bumping applications since a pitch of less than 400 microns is required.
AT&T has used stencil printing to produce silicon-on-silicon assemblies. The process involves mounting the mask, joining the silicon to silicon with stenciled paste between the silicon components, and reflowing, thereby producing a silicon-on-silicon attach. The mask apertures are limited by the aspect ratio.
Serial methods have been proposed, and while attractive in theory, none has been commercialized. Proposed methods have included "stud-bumping" with wirebonding equipment (also known as "wirebond bumps"), decal processing, and solder jet processes. Methods proposed to simplify serial processes still require multiple steps. U.S. Pat. No. 5,156,997 issued to Kumar et al. describes a simplified process consisting of depositing a barrier and diffusion layer, forming a bump from a metal using a focused liquid metal ion source, and removing the exposed barrier/adhesion layer by etching. The process takes over 13 hours to bump a 200 die wafer. Thus, even simplified serial processing has associated processing disadvantages such as slow throughput.
A dramatic and significant improvement would be a simple, low cost, high volume, environmentally friendly (or environmentally neutral), non-hazardous process for applying bumps of various alloys to substrate where the bumps are uniform in height and the pitch small, and, ideally, such a method would provide bump alloys that are compatible with existing surface mount technology assembly lines.